In order to drive a large bus load on an integrated circuit chip, generally three or more levels of buffering are needed because of the relatively large load the bus presents to the driving circuit. The data enabling signal must be synchronized with the system clock. A transistor-transistor-logiq (TTL) compatible clock applied to a pad with a protection device is the most common way of inputting a clock signal into a VLSI integrated circuit chip. This clock signal will go through two or more levels of buffering to obtain the metal oxide semiconductor (MOS) logic level and driving capability. However, each additional stage of buffering induces an additional delay and slows down the bus driver.
According to the present invention, a minimum delay high speed tri-state bus driver is utilized to couple the data and control signals to the memory bus with a minimum amount of buffering. Two transistors, utilizing the bootstrap configuration, deliver the system clock to the gates of the output transistors which are coupled to the memory output bus. The input data signal and accompanying control signals are applied to these bootstrap transistors and, depending on the data level of the input data signal, either a logic 1, a logic 0, or a high impedance open circuit is applied to the bus.